Variable length instruction set architectures are known in the art. For example, when the Thumb (16-bit) extensions are added to the ARM (32-bit) instruction set, the resulting mix may be considered a variable length instruction set. As another example, executable Java code comprises a series of bytecodes, with each instruction ranging between 2 and 256 bytes in length. In general, variable length instruction sets comprise instructions of a base size, and longer instructions that are an integral multiple of the base size.
Processor architectures and instruction sets evolve over time. In particular, as semiconductor technology advances, functionality may be rendered in hardware that formerly required an extensive software routine to accomplish. To efficiently exploit the advanced hardware structures, new instructions are added to the instruction set. However, one feature of stable processor architectures is backward compatibility. That is, software written for a processor architecture should be executable on an older processor that conforms to the architecture, even if it does not implement the most recent functionality or directly execute the most recent instructions. Accordingly, common processor architectures include an “undefined” instruction which generates an exception, and the function associated with the undefined instruction is executed in software.
One common approach taken by conventional high-performance processors to optimize instruction decoding is pre-decoding. A pre-decoder is a logic circuit that inspects and partially decodes instructions fetched from memory prior to storing the instructions in an instruction cache (I-cache). The pre-decoder generates a small number of pre-decode bits that are stored along with each instruction in the I-cache. Upon fetching instructions from the cache, the pipeline decoder may utilize the pre-decode bits to simplify the instruction decoding task. Pre-decode bits may, for example, identify branch instructions, identify the length of an instruction in a variable length instruction architecture, or the like. Pre-decode bits may also be utilized to identify undefined instructions.
In a variable length instruction set processor that implements pre-decoding, a small number of pre-decode bits may be associated with the shortest, or base, instruction length. A known instruction cache implementation is to associate this number of pre-decode bits with each I-cache storage location (each of which corresponds to the base instruction length). Longer instructions, occupying an integral multiple of I-cache storage locations, are correspondingly associated with a larger number of pre-decode bits. The number of discrete properties that can be encoded into the pre-decode bits associated with an instruction is thus a minimum for the base instruction length. If all of the available pre-decode bit encodings of the base instruction length are otherwise defined, utilizing the pre-decode bits to identify an undefined base length instruction would require increasing the number of pre-decode bits associated with the base instruction length. This technique would in turn increase the number of pre-decode bits stored along with every storage location in the I-cache. Since undefined instructions are rarely encountered, and instructions longer than the base length have a rich pre-decode bit encoding space, adding pre-decode bits to identify undefined base length instructions can waste expensive I-cache storage space.